1. Field of the Invention
This invention relates to a process for fabricating oxide isolated integrated injection logic structures. In particular, the process of the present invention relates to a method for forming oxide isolated vertical bipolar transistors, complementary lateral bipolar transistors, or composite bipolar transistors merging both vertical and lateral bipolar transistors.
2. Prior Art
Integrated circuit structures utilizing injection logic, commonly referred to as I.sup.2 L (for "integrated injection logic"), are known in the semiconductor arts. In particular, it is known that integrated injection logic structures reduce a gate to a complementary transistor pair which may be integrated into a single device if a lateral transistor is used as a current source for the base of a vertical transistor which is operating in an inverse mode. See, e.g., the references collected in U.S. Pat. No. 3,993,513 issued to O'Brien on Nov. 23, 1976, and titled "Combined Method for Fabricating Oxide Isolated Vertical Bipolar Transistors and Complementary Oxide Isolated Lateral Bipolar Transistors and the Resulting Structures."
Further, semiconductor processing technologies are known which may be utilized to fabricate such oxide isolated structures. See, e.g., the process technology described in O'Brien, supra. Unfortunately, such prior art processing technologies have several drawbacks. Typically such processes utilize several steps in which vapor deposited silicon dioxide (also known as vapox) is used. Applicants have discovered that this use of vapox frequently leads to defects in the semiconductor structure known as pinholes. Additionally, the use of vapox results in an unnecessarily large encroachment silicon pocket. In prior art processes for making I.sup.2 L structures, the etching of the vapox after etching the epitaxial silicon layer in the field regions would remove much of the thin layer of silicon dioxide typically formed beneath the silicon nitride layer used for masking. This undercutting increased the encroachment of the field oxide into the epitaxial silicon pocket during formation of the field oxide. The encroachment frequently led to an emitter walling effect (described below) which caused an undesirably great amount of emitter-collector leakage. Further, prior art processing technology typically created structures with regions of silicon nitride and vapox remaining on the wafer surface. The presence of these layers created an uneven rough topography which made difficult the subsequent reliable fabrication of metal lines for electrical interconnections.
It is therefore an object of this invention to fabricte oxide isolated integrated injection logic structures in which vapox is not used for defining the various regions in the integrated circuit, in which encroachment of the field oxide into the device regions is minimized, in which a smoother more uniform topography is created, and in which fewer processing steps are used to fabricate a completed device structure.